Storage

FPGA Based Complex Test Pattern Generation for High Speed Fault Diagnosis in FPGA Based Memory Blocks

Free registration required

Executive Summary

The memory blocks testing is a separate testing procedure followed in VLSI testing. The memory blocks testing involve writing a specific bit sequences in the memory locations and reading them again. This type of test is called March test. A particular March test consists of a sequence of writes followed by reads with increasing or decreasing address. There are several test circuits available for testing the memory chips. However no test setup is developed so far for testing the memory blocks inside the FPGA. The BRAMs of FPGA are designed to work at much higher frequency than the FPGA core logic.

  • Format: PDF
  • Size: 490 KB