FPGA-Based, Multi-Processor HW-SW System for Single-Chip Crypto Applications
This paper discusses design and analysis of an FPGA-based system containing two isolated, Altera Nios II softcore processors that share data through two custom cryptoengines. FPGA-based Single-Chip Cryptographic (SCC) techniques were employed to ensure full red/black separation. Each crypto-engine is a hardware implementation of the Advanced Encryption Standard (AES), operating in Galois/Counter Mode (GCM). The features of the AES crypto-engines were varied with the goal of determining which best achieve high performance or minimal hardware usage. To quantify the costs of red/black separation, a thorough analysis of resource requirements was performed.