FPGA Design Methodology for Time Domain Dead Beat Algorithm
In this paper, the authors propose a way of implementing a deadbeat controller in FPGA. The focus is on the FPGA implementation of the digital controller. The emphasis is on the software tools for design and simulation of FPGA based hardware for control applications. The FPGA is interfaced to the controlled process by means of serial Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC). The deadbeat regulator output can be depicted: a strong command at the first sample when the reference signal change is observed followed by smaller changes and reaching stationary value after 3 sample periods. A method to implement a deadbeat controller in an FPGA was presented.