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In this paper, the authors present a FPGA implementation of Single Carrier (SC) wireless system with Frequency Domain Equalization (FDE) to overcome the effects of multipath fading channels. They propose a new packet format for this wireless system to reduce the error of channel estimation that occurs in the last part of the packet caused by time fluctuation of the channel. Their targets are veracity 15 km/h and 3 Mbps data rate under 1MHz bandwidth. Simulation results show that their proposed system can work in severe multipath fading with 33 Hz Doppler shift (15km/h) and 6 ppm frequency offset environment. The logic synthesis result meets the specification.
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