FPGA Implementation of a LDPC Decoder Using a Reduced Complexity Message Passing Algorithm

In this paper, a simplified message passing algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity. The algorithm is based on simple hard-decision decoding techniques while utilizing the advantages of soft channel information to improve decoder performance. It has been validated through simulation using LDPC code compliant with Wireless Local Area Network (WLAN - IEEE 802.11n) standard. The results show that the proposed algorithm can achieve significant improvement in Bit Error Rate (BER) performance and average decoding iterations compared to fully hard-decision based decoding algorithms.

Provided by: Academy Publisher Topic: Mobility Date Added: Jan 2011 Format: PDF

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