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FPGA Implementation of Systolic Array Architecture for 3D-DWT Optimizing Speed and Power

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Executive Summary

Demand for high speed and low power architectures for image/video compression algorithms are increasing with scaling in VLSI technology. Video sequences are considered as 3D sequences and are compressed using 3D DWT architectures. In this paper, systolic array architectures for 2D DWT have been modified and have been used in computing 3D DWT and 3D IDWT. The architecture uses intermediate memories efficiently in storing the intermediate coefficients and a memory control module controls the data path operation. The systolic array is designed with a constant coefficient multiplier and a fast adder to realize the accumulator. Daub-8 wavelet is used to compute DWT sub bands; the coefficients are scaled and stored in memory for processing of input in all three dimensions.

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