FPGA Implementation of USB 2.0 Receiver Protocol

The Universal Serial Bus (USB 2.0) is support data exchange between a host computer and a wide range of simultaneously accessible peripheral like mouse, keyboard, digital camera, printer, scanner, etc. The USB 2.0 supported three types of data transmission rates; those are operated low speed (1.5MHz), high speed (12MHz) and full speed (480MHz). In this paper, the authors' coverage is up to implementation of USB 2.0 receiver protocol on FPGA kit (SPARTAN-II XC2S200). The FPGA design of USB 2.0 receiver protocol provides an interface for 'System-on-chip' designer to connect UBS bus.

Provided by: Seek Digital Library Topic: Hardware Date Added: Oct 2012 Format: PDF

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