FPGA Implementation of Viterbi Decoder Using Trace Back Architecture
Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes. For decoding of convolution codes, at the receiver end Viterbi Decoder is being employed. The parameters of Viterbi algorithm can be changed to suit a specific application. The high-speed and small area is two important design parameters in today's wireless technology. In this paper, a high-speed feed forward viterbi decoder has been designed using track back architecture and embedded BRAM of target FPGA.