FPGAC: - High Level Synthesis Tool
The rapidly increasing System-on-Chip (SoC) complexity is forcing researchers to shift from RTL and raise the level of abstraction, i.e. opting for High Level Synthesis (HLS). Despite failures of starting generations of commercial high level synthesis tools. The authors strongly believe that current time is turning point for shifting to HLS methodology, especially in the field of FPGA's designing. Current generation of High Level Synthesis tools (HLS) have made enormous progress in providing support for various programming language, robust compilation, optimization and GUI based tools.