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This paper present a Xilinx Virtex-5 FPGA implementation of a low power Spatial Modulation (SM) based transmitter for the Multiple-Input Multiple Output (MIMO) systems. The low power consumption is achieved using fractional bit encoding and a data dependency check before the spatial multiplexing. This data dependency check allows efficient selection of antennas for parallel transmission of data while the Fractional Bit Encoding (FBE) is modulus conversion scheme which convert the incoming bit stream to numbers in an arithmetic base, or modulus, that is not a power of 2.
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