Frequent Value Compression in Packet-Based NoC Architectures

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Executive Summary

The proliferation of Chip Multi-Processors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller banks that are interconnected through packet-based Network-on-Chip (NoC). With increasing number of cores and cache banks integrated on a single die, the on-chip network introduces significant communication latency and power consumption. In this paper, the authors propose a novel scheme that exploits Frequent Value compression to optimize the power and performance of NoC. Their experimental results show that the proposed scheme reduces the router power by up to 16.7%, with CPI reduction as much as 23.5% in their setting.

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