Download now Free registration required
Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the Maximum A Posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This paper introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards.
- Format: PDF
- Size: 741.89 KB