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Godson-3s scalable and distributed on chip network connects processor cores and globally addressed level-two (L2) cache modules. A directory-based cache-coherence protocol maintains multiple level-one (L1) copies of the same L2 block. Godson-3's MIPS64-compatible superscalar reduced instruction-set-computing (RISC) processor core is designed for high performance and low power dissipation. It also supports efficient x86 to MIPS binary translation through dedicated hardware support. Godson-3 adopts the scalable mesh of crossbar (SMOC) on-chip network topology. Using the SMOC architecture, a 2 2 mesh network can support a 16-core processor, and a 4 4 mesh network can support a 64-core processor.
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