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The authors have performed the first order analysis of the influence of the Round 3 tweaks in Groestl on the performance of this algorithm in FPGAs. Both Groestl-0 and the revised Groestl have been fully implemented in VHDL using two alternative architectures: quasi-pipelined and parallel. The results indicate that the performance penalty in terms of the throughput to area ratio depends strongly on the architecture used. In case of the quasi-pipelined architecture, they have observed from 29% to 38% decrease in the throughput to area ratio for Altera and Xilinx FPGAs. For the parallel architecture, they expected much smaller penalty.
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