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How can a designer accurately predict the time delays of a fully customizable integrated circuit? The answer to this question is "Not very easily." There are many factors that limit and increase the complexity of accurately modeling time delays in an integrated circuit. A few of these factors include, but are not limited to large space of valid operating conditions (voltage, temperature, process, etc.), complex physical phenomena with (often) non-linear and complicated models, and variability of mass-produced silicon. Altera has devised a method to accurately predict the time delays for all designs implemented in its FPGAs.
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