Guiding Architectural SRAM Models

Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Making good architectural decisions early in the design process requires a reasonably accurate model for these important structures. Dealing with continuously changing SRAM design practices and VLSI technologies make this a very difficult problem. Most hand-built memory models capture only a single parameterized design and fail to account for changes in design practice for different size memories or problems with wire scaling. Instead, in this paper the authors present a high level model that can be used to make simple analytical estimates. The model is built using the characterization of almost 60 real memory designs from the past 15 years.

Provided by: University of California Topic: Hardware Date Added: Jan 2011 Format: PDF

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