Handling Shared Variable Synchronization in Multi-Core Network-on-Chips With Distributed Memory

Date Added: Jul 2010
Format: PDF

Parallelized shared variable applications running on multi-core Network-on-Chips (NoCs) require efficient support for synchronization, since communication is on the critical path of system performance and contended synchronization requests may cause large performance penalty. In this paper, the authors propose a dedicated hardware module for synchronization management. This module is called Synchronization Handler (SH), integrated with each processor memory node on the multi-core NoCs. It uses two physical buffers to concurrently process synchronization requests issued by the local processor and remote processors via the on-chip network.