Hardware and Interface Synthesis of FPGA Blocks Using Parallelizing Code Transformations

Reconfigurable logic such as FPGAs is increasingly being used on System-on-Chip (SoC) platforms to provide a flexible, programmable co-processor that augments the core processor. In this paper, the authors present a tightly coupled hardware synthesis and interface synthesis approach that forms part of the hardware-software co-design methodology for such FPGA-based platforms. For hardware synthesis, they use a parallelizing high-level synthesis approach that employs aggressive coarse-grain and fine-grain code parallelizing and code motion techniques to discover circuit optimization opportunities beyond what is possible with traditional high-level synthesis. They have implemented this approach in a framework called Spark that takes a behavioral description in ANSI-C as input and produces synthesizable register-transfer level VHDL.

Provided by: UC Regents Topic: Data Centers Date Added: Jan 2011 Format: PDF

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