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Until recently, embedded systems were often built with computing blocks containing a single CPU. Each block included a processor, memory controller and I/O bridge. This model has been a long-lived one. As applications demanded additional performance, Moore's Law delivered ever faster and more sophisticated processors and bridge silicon. In return, power dissipation grew as clock-rates and silicon leakage increased with each generation of silicon technology. Recently, an industry-wide consensus has emerged that physics no longer allows increasing clock rates within practical power envelopes. To deliver increasing performance, a similar consensus has arisen on the value of offering multiple processing cores at limited clock rates in place of single cores running at significantly higher clock rates.
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