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In conventional memory-based multiplication design, the multiplier is replaced by a read only memory (ROM). Since the memory size increases exponentially with the input length, in this paper, a modified hardwareefficient approach for memoryless-based multiplication is proposed. The very large scale integration (VLSI) measure indicates that the proposed approach involves less hardware complexity compared with the existing one. Then the proposed approach is applied in the finite impulse response (FIR) filter. It is observed that the proposed memorylessbased multiplication can be decomposed into a number of small units.
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