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In recent times, DSP algorithms have received increased attention due to rapid advancements in multimedia computing and high-speed wired and wireless communications. In response to these advances, the search for novel implementations of arithmetic-intensive circuitry has intensified. For the portability requirement in telecommunication systems, there is a need for low power hardware implementation of fast fourier transforms algorithm. This paper proposes the hardware implementation of low power multiplier-less radix-4 single-path delay commutator pipelined fast fourier transform processor architecture of sizes 16, 64 and 256 points. The multiplier-less architecture uses common sub-expression sharing to replace complex multiplications with simpler shift and add operations.
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