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Hardware Implementation of DWT for Image Compression Using SPIHT Algorithm

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Executive Summary

In this paper, a DWT-based image processing system is developed on Xilinx Spartan3 Field Programmable Gate Array (FPGA) device using Embedded Development Kit (EDK) tools from Xilinx. Two different hardware architectures of Two Dimensional (2-D) DWT have been implemented as a coprocessor in an embedded system. One is direct implementation of 2-D DWT by cascading two 1-D DWT. Another is 2-D DWT implementation with control and architecture optimization. In addition, the hardware cost of these two architectures is compared for benchmark images.

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