HDL Implementation and Performance Comparison of an Optimized High Speed Multiplier

In this paper, the authors is devoted for the design of an optimized high speed Vedic multiplier using Udhava-Tiryakbhyam sutra. High speed multiplier is required to perform critical multiplication operation of digital signal processing applications like DFT,FFT, convolution, Arithmetic and Logic Unit (ALU) and Multiply and ACcumulate (MAC). This paper shows the Multiplier architecture for 2×2, 4×4, 8×8 and 16×16 .The performance has been evaluated in XILINX ISE 9.2. Synthesis and simulation have been performed for various architectures considering delay, number of slices, power and area.

Provided by: Iosrjournals Topic: Hardware Date Added: Apr 2015 Format: PDF

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