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Low-Density Parity-Check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. These codes offer huge advantages in terms of coding gain, throughput and power dissipation. Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However hardware implementation of LDPC decoders using traditional Hardware Description Language (HDL) based approach is a complex and time consuming task.
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