Heat Spreading Aware Floorplan for Chip Multicore Processor
With more cores integrated into one chip and multiple threads running concurrently on the chip, power consumption from the running threads increases dramatically, and then causes the thermal of the chip going much higher than before. Existed schemes to leverage the thermal problem for a chip multi-core processor include DVFS, Clock Gating, thread migration, and so on. In this paper, the authors propose a new architectural method to address the thermal problem from another perspective, the floorplan of the multi-core chip. Their method exploits the heat spreading model of a chip and tries to come up with a floorplan for a multi-core processor which leaves the potential hotspots in different cores as far away from each other as possible.