Hardware

High level modeling of Dynamic Reconfigurable FPGAs

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Executive Summary

As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction of new seamless methodologies and tools to handle the SoC co-design aspects. This paper presents a novel SoC co-design methodology based on Model Driven Engineering and the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) standard, permitting one to raise the abstraction levels and allows to model fine grain reconfigurable architectures such as FPGAs.

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