High Performance Error Detection and Correction for Memory Applications Using Majority Logic Decoder and Detector
The error-detection and correction method for difference-set cyclic codes with majority logic decoder and detector is to be present in this paper. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. They require a large decoding time that impacts memory performance. The fault detection method significantly reduces memory access time when there is no error in the read data. This technique using the majority logic decoder itself to detect errors, it makes the area overhead minimum and keeps the extra power consumption low.