High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications
In this paper, the authors present a high PSRR full on-chip and area efficient Low Drop-Out voltage regulator (LDO), exploiting the Nested Miller Compensation technique with Active Capacitor (NMCAC) to eliminate the external capacitor. A novel technique is used to boost the important characteristic for wireless applications regulators PSRR. The idea is applied to stabilize the low dropout regulator. The proposed regulator LDO works with a supply voltage as low as 1.8 V and provides a load current of 50 mA with a dropout voltage of 200 mV.