Hardware

High Speed 3D Tomography on CPU

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Executive Summary

Back-Projection (BP) is a costly computational step in tomography image reconstruction such as Positron Emission Tomography (PET). To reduce the computation time, this paper presents a Pipelined, Prefetch, and Parallelized Architecture for PET BP (3PAPET). The key feature of this architecture is its original memory access strategy, masking the high latency of the external memory. Indeed, the pattern of the memory references to the data acquired hinders the processing unit. The memory access bottleneck is overcome by an efficient use of the intrinsic temporal and spatial locality of the BP algorithm. A loop reordering allows an efficient use of general purpose processor's caches, for software implementation, as well as the 3D Predictive and Adaptive cache (3D-AP cache), when considering hardware implementations.

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