High Speed and Area Optimized Floating Point FPGA Architecture
In this paper, an architecture for a reconfigurable device is proposed that is specifically designed for floating-point applications. Fine-grained units are used for implementing control logic and bit-oriented operations. Reconfigurable word-based coarse-grained units are word-oriented lookup tables. Floating-point operations are used to implement data-paths. This methodology involves adopting existing FPGA resources to model the size, position, and delay of the embedded elements. The standard design flow offered by FPGA and computer-aided design vendors is then applied. This proposed circuit indicates that the proposed architecture can achieve four times improvement in speed and 25 times reduction in area compared with a traditional FPGA device.