High Speed Booth Encoded Multiplier by Minimising the Computation Time
Two's complement multipliers are used in most of the applications. The computation time is important in two's complement multiplier. The computation time gets decreased by reducing the number of gates. The reduction can be achieved by modified booth encoded multiplier technique. Two's complement multipliers are used in wide range of applications like multimedia, 3D graphics, signal processing etc. In this paper one row of the partial product array can be reduced without increasing the delay. This MBE technique allows faster computation of the partial product array which is used in most of the multiplier designs.