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High-speed Hardware Implementation of Rainbow Signatures on FPGAs

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Executive Summary

The authors propose a new efficient hardware implementation of Rain-bow signature scheme. They enhance the implementation in three directions. First, they develop a new parallel hardware design for the Gaussian elimination to solve a n x n linear system with only n clock cycles. Second, a novel multiplier was designed to speed up multiplication of three elements over a finite field. Third, they further optimize the parallelization process of the hardware to generate the Rainbow signature. By integrating these optimizations, they build a new hardware implementation, which takes only 198 clock cycles to generate a Rainbow signature, a new record in generating digital signatures and four times faster than the 804- clock-cycle Balasubramanian-Bogdanov-Carter-Ding-Rupp design with similar parameters.

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