High Speed Vedic Multiplier in FIR Filter on FPGA
Digital Signal Processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very important in DSPs for convolution, Fourier transforms etc .In this paper a fast method for multiplication based on ancient Indian Vedic mathematics is used in FIR filter design .The proposed Vedic multiplier is based on Vedic multiplication sutras. Vedic multiplication based on Urdhva tiryakbhyam sutra. This algorithm is applied to digital arithmetic and multiplier architecture is formulated. The coding is done in VHDL (Very high speed integrated circuits Hardware Description Language) and synthesis is done using Xilinx ISE series.