Highly Accelerated Advanced Multiplier Design for an Efficient Bandwidth Utilized FFT Computation
Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in general purpose processors today especially since the media processing took off. The authors present a Fast fourier transform implementation using Twin precision technique. The twin precision technique can reduce the power dissipation by adapting a multiplier to the bit width of the operands being computed. The algorithm used here is Baugh-Wooley algorithm. By adapting to actual multiplication bit-width using twin precision technique, it is possible to save power, increase speed, double computation throughput and highly efficient.