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As microprocessors continue to evolve many optimizations reach a point of diminishing returns. The authors introduce HLS, a hybrid processor simulator which uses statistical models and symbolic execution to evaluate design alternatives. This simulation methodology allows for quick and accurate contour maps to be generated of the performance space spanned by design parameters. They validate the accuracy of HLS through correlation with existing cycle-by-cycle simulation techniques and current generation hardware. The authors demonstrate the power of HLS by exploring design spaces defined by two parameters: Code properties and value prediction.
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