Identification of Highly Jittered Radar Emitters: Issues on Low Cost Embedded Design
This paper presents efforts toward design of radar identification system for highly jittered radar emitters. The paper first provides a mathematical background of clustering techniques, and then presents a derivation of additional parameters, such as PRI, among mixed pulse sequence and, finally, discusses implementation of digital processing part on a low cost standard Field Programmable Gate Array (FPGA) environment. The system is designed for radar emitters with stable PRI. Identification of radar emitters, or threats in military jargon, has been important with the advances in RF, electronics and computing technologies.