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Over the past few years, Chip Multi Processor (CMP) architecture has become the dominating hardware architecture across a spectrum of computing machinery - personal computing devices, workstations, commercial and scientific servers, and warehouse scale computers. The sheer complexity involved in the design and verification of each unit in a CMP solution has necessitated significant design reuse. In this paper, the authors study the effect data and instructions sharing on cache miss rates. They then extend an analytical system-level throughput model to take multi-threaded data and instruction sharing into account. They use the model to provide insights into the interaction of thread count, cache size, off-chip bandwidth, and, sharing, on system throughput.
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