Impact of Faulty Links on Quality-of-Service in Network-on-Chip Under Different Traffic Patterns

Download Now Free registration required

Executive Summary

Through Network-on-Chip (NoC) architecture, organizations are now able to run multiple applications on IP-core based System on Chip simultaneously. This calls for predicting the multi-processor systems-on-chip communication, which can be done through a right mix of soft and hard real-time guarantees. Meeting these requirements are state of the art packet switched NoC that offers different levels of Quality of Service (QoS) such as Best Effort (BE) and Guaranteed Throughput (GT).This document attempts to take up this subject by introducing the impact of faulty links on Quality of Service in Network-on-Chip (NoC) under different traffic pattern. The paper compares and evaluates the performance of guaranteed throughput and best effort traffic in Network-on-Chip under different synthetic traffic generators. In the process, the document also highlights its dependence in terms of latency on the type of traffic patterns and number of link failures for mesh topology. The white paper also studies the variation in average latency with the increase in the number of link failures. The conclusion arrived at the end of the paper states that with lower average latency for both BE and GT classes in shuffle traffic there was a increase in number of link failures. This implied that it is more fault tolerant. On the other hand, Bit complement traffic pattern is least fault tolerant as it experiences a higher value of average latency with the increase in number of link failures.

  • Format: PDF
  • Size: 144.4 KB