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In order to satisfy the needs for increasing computer processing power, there are significant changes in the design process of modern computing systems. Major chip-vendors are deploying multicore or manycore processors to their product lines. Multicore architectures offer a tremendous amount of processing speed. At the same time, they bring challenges for embedded systems which suffer from limited resources. Various cache memory hierarchies have been proposed to satisfy the requirements for different embedded systems. Normally, a Level-1 Cache (CL1) memory is dedicated to each core. However, the Level-2 Cache (CL2) can be shared (Like Intel Xeon and IBM Cell) or distributed (Like AMD Athlon).
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