Implementation and Optimisation of FPGA Based Network Security System Using VHDL
The combination of traditional microprocessors and Field Programmable Gate Array(FPGAs) is developing as a future platform for intensive computational computing, combining the best aspects of traditional microprocessor front-end development with the re-configurability of FPGAs for computation-intensive problems. This paper present the IDEA algorithm with regard to FPGA and the very high speed integrated circuit hardware description language. Synthesizing and implementation of the VHDL code carried out on Xilinx project navigator, ISE suite. Experimental measurement result show that the proposed design is faster and smaller and also consume less power than similar hardware implementation making it a viable option for efficient This paper talks of IDEA 64 bit plain text, 128 bit key and 64 bit cipher text.