Hardware

Implementation of a Bit Error Rate Tester of a Wireless Communication System on an FPGA

Date Added: May 2014
Format: PDF

In this paper the authors deal with the Field Programmable Gate Array (FPGA) implementation of an entire digital baseband wireless communication system. The proposed BER Tester (BERT) integrates the modules of a typical communication system along with an AWGN channel into a single FPGA. The BER is calculated for a 22 MIMO system also. This FPGA based solution is a more cost effective, flexible and faster solution compared with the commercially available BER test equipments and software based simulators.