Implementation of a Reconfigurable ASIP for High Throughput Low Power DFT/DCT/FIR Engine
In this paper, the authors present an ASIP design for a Discrete Fourier Transform (DFT)/Discrete Cosine Transform (DCT)/Finite Impulse Response filters (FIR) engine. The engine is intended for use in an accelerator-chain implementation of wireless communication systems. The engine offers a very high degree of flexibility, accepting and accelerating performance approaches that of any-number DFT and inverse discrete fourier transform, one and two dimension DCT, and even general implementations of FIR equations. Performance approaches that of dedicated implementations of such algorithms. A customized yet flexible redundant memory map allows processor-like access while maintaining the pipeline full in a dedicated architecture-like manner.