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Advanced Encryption Standard has received significant interest over the past decade due to its performance and security level. Many hardware implementations have been proposed. In most of the previous papers, sub-bytes and inverse sub-bytes are implemented using lookup table method. In this paper, the authors used combinational logic which helps for making intra-round pipelining in an efficient manner. Furthermore, composite field arithmetic helped in obtaining lesser area. Using proposed architecture, a fully sub pipelined encryptor/decryptor with 4 sub-pipelining in each round can achieve a throughput of 21.54 Gbps on Xilinx xc5vlx110t-1 device which is faster and is 47% more effective. This AES design was implemented using VHDL and synthesized using ModelSim 6.3f and achieved the maximum through put of 21.54 Gbps.
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