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Power consumption has become one of the biggest challenges in design of high performance microprocessors. In this paper, the authors present a design technique using GALs (Globally-Asynchronous Locally-Synchronous) for implementing asynchronous ALUs, which aims to eliminate the global clock. Here ALUs are designed with delay insensitive dual rail four phase logic and CMOS domino logic. It ensures economy in silicon area and potentially for low power consumption. This has been described and implemented in order to achieve a high performance in comparison with synchronous and available asynchronous design. Also simulation results, show significant reduction in the number of transistors as well as delay.
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