Implementation of AXI Design Core With DDR3 Memory Controller for SoC
This paper discusses the overall architecture of AMBA AXI design core along with its advantage with DDR3 memory controller and operation of its individual sub blocks. It takes care of the DDR3 initialization and various timing requirements of the DDR3 memory. The memory controller works as an intelligent bridge between the AXI host and DDR3 memory. The authors' design has been implemented with respect to latency reduction and improvement in various performance parameters and the design is simulated on Modelsim and synthesized on Xilinx successfully.