Implementation of Binary Multiplication using Booth and Systolic Algorithm on FPGA using VHDL
In mathematics, multiplication is the most commonly used operation. Though integer multiplication is used commonly in the real world, binary multiplication is the basic multiplication used for the integer multiplication. Systolic and Booth algorithms are the efficient algorithms to perform the binary multiplication. In this paper, an attempt is made to implement the prototype of binary multiplier using Booth algorithm (for signed number) and the systolic array multiplication algorithm (for unsigned number). This is implemented using Xilinx ISE6 software, simulated using Modelsim XE 5.5a simulator by mentor graphics.