Implementation of Combinational Automatic Test Pattern Generator D-Algorithm
Testing of combinational circuit is crucial important to ensure high level of functionality. As density of digital circuit increases rapidly day-by-day these increases cost and time to test a particular combinational circuit for testing such circuit the authors need high quality test vector pattern with minimum number of input combination. In this paper, they are designing Automatic Test Pattern Generator (ATPG) D-algorithm which will generate a minimum number of input patterns to detect fault like stuck-at-0 fault, stuck-at-1 fault and short circuit fault. D-algorithm has been design by writing practical extraction and report language script to generate VHDL coding which is simulated on Xilinx 9.1.