Processors Investigate

Implementation of GALS Chip Multiprocessor With Flexibly Configurable Low Latency Interconnect

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Executive Summary

Chip Multiprocessors with flexible configuration capability and with reduced latency is implemented in FPGA with reduced area utilization. Globally Asynchronous Locally Synchronous (GALS) design style helps to reduce the power consumption. Improved the number of logic realization by having multiple ports for the processor core. Low latency is achieved through asymmetrically buffered static routing mechanism that allocates larger buffer for the processing core and smaller buffer for the output ports of the processor in the implemented chip multiprocessor. Compared to the traditional dynamically routed architecture it is occupying less area and maintained the flexibility in routing by assigning double link between nearest neighbor processor pairs.

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