Hardware

Implementation of Generic Algorithm Using VHDL on FPGA

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Executive Summary

The development of a flexible Very-Large-Scale Integration (VLSI) for GA has been proposed in this paper. For the hardware architecture, the authors have develop on a Random Number Generator (RNG), crossover, and mutation based on flexibility structure. This structure can dynamically perform to the 3 types chromosome encoding: binary encoding, real-value encoding, and integer encoding. The overall structures has been designed and synthesized by VHDL (VHSIC Hardware Description Language), simulation by ModelSim program, and then implemented on FPGAs (Field Programmable Gate Arrays). This hardware architecture that their design work very well flexible for the 3 groups problem examples: combinatorial optimization problems, function optimal problems.

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