Implementation of Neural Network Back Propagation Training Algorithm on FPGA
This paper presents the implementation of trainable Artificial Neural Network (ANN) chip, which can be trained to implement certain functions. Usually training of neural networks is done off-line using software tools in the computer system. The neural networks trained off-line are fixed and lack the flexibility of getting trained during usage. In order to overcome this disadvantage, training algorithm can implemented on-chip with the neural network. In this paper back propagation algorithm is implemented in its gradient descent form, to train the neural network to function as basic digital gates and also for image compression.